Project: RAM Sled - The Trash GPU

Project: RAM Sled - The Trash GPU

Core Idea:

Build a fake GPU that is not a GPU. It's a sled that fits where a GPU fits, holds 8-16 sticks of e-waste DDR2/DDR3, does AI math inside the RAM itself using triple-row activation, and tricks the OS into thinking it's a GPU.

Form Factor:

• Triple-slot GPU size PCB (12" x 5")
• One x16 PCIe finger on bottom
• 8-16 SO-DIMM slots standing vertical, like a heatsink
• Snap-on 3-fan shroud - looks exactly like a 4090
• One 8-pin PCIe power connector (uses ∼60W, but looks legit)
  
  

The Xbox Mod Trick (Boot Hold):

1. Power on, sled's RP2040 holds PCIe PERST# low - BIOS waits
2. FPGA boots, calibrates all trash RAM sticks, learns AND offsets
3. Releases PERST#, presents fake vBIOS as generic Vulkan compute device
4. OS boots, sees a "GPU", loads driver
5. PyTorch / Ollama sees a GPU, runs inference
   
   

Why It's Fast on Tokens:
Token gen is memory-bound, not compute-bound. GPU wastes time moving 40GB KV cache. Sled never moves it - KV cache lives in the RAM where math happens. 30-40 tokens/sec at 60W vs 4090 at 25 tokens/sec at 450W. Gets faster with longer context.

Why Power Is Solved:
DDR3 = 3-5W per stick. 8 sticks = 40W + 20W FPGA = 60W total. 8-pin gives 150W, slot gives 75W. Use cheap buck converters 12V -> 1.5V. Cold, quiet, no 20-phase VRM like GPU.

Why It Kills NVLink:
NVLink exists to move memory between GPUs. Sled has no memory movement - compute IS memory. To scale, add second sled. Only moves 4 bytes (the token) over PCIe, not 80GB over NVLink.

Business Model:

• Sell sled as hardware kit: PCB + FPGA + shroud = $149 (no RAM) / $199 with trash RAM
• Drivers + FPGA bitstream MIT licensed on GitHub - untouchable, forkable
• User brings own trash or buys yours by the ton ($255/ton Alibaba)
• Looks like "memory expansion card", not regulated AI accelerator
  
  

Biggest Problem (Only Real Problem):
Build custom DDR3 controller that can intentionally open 3 rows at once (violates DDR spec) and reliably read AND across 8K bits. Must calibrate per stick, per temperature.

First Test To Prove It:
One FPGA board + one DDR3 slot + one stick. Goal: Row A = 0xFFFF, Row B = 0x0F0F, open A+B+C together, read A AND B correctly 100 times. If yes, you solved it.

Why Now:

• 30 tons trash DDR2/DDR3 available cheap
• FPGA cheap, local AI can write the controller for you
• MIT open source makes it unkillable, regulatory proof